Field of the Invention
The invention relates to a device for selecting a level for at least one read voltage for reading data stored in a multi-level memory device, a memory system including a multi-level memory device, and a device. Further, the invention relates to a method for selecting a level for at least one read voltage for reading data stored in a multi-level memory device and to a computer program for executing such a method. More specifically, the multi-level memory device includes multi-level cells (MLC) having a plurality of programmable levels.
Background
A prominent example for MLC memory cells having a plurality of programmable levels is Resistive Random Access Memory (RRAM; see A Multi-Level 40 nm WOx Resistive Memory with Excellent Reliability by Wei-Chih Chien et al.), Phase Change Memory (PCM; see Phase Change Memory by H.-S. Phillip Wong et al.), or Flash (see Nonvolatile Multilevel Memories for Digital Applications by Bruno Ricco et al.). PCM is a non-volatile solid-state memory technology that exploits a reversible, thermally-assisted switching of specific chalcogenides between certain states of different electrical conductivity.
A multi-level memory device typically includes a plurality of memory blocks. Each memory block includes a plurality of word lines. The word lines include each a plurality of memory cells within which one or more pages are interleaved. In order to read data stored in the pages, a number of read voltages are applied to the word lines. In order to extend the endurance of the memory cells, the read voltage should be kept at an optimal level. In principle, the criterion used to determine the optimal levels can vary. For instance, the optimal read voltages can be defined to be those voltages that minimize the raw bit error rate at the output of the multi-level memory device. Over the course of the lifetime of the memory cells, the optimal read voltage levels change.
In common systems, a static table of read voltage levels is used to choose a read voltage level. The stored read voltage levels are indexed by a program/erase (P/E) cycle count. The P/E cycle count refers to the number of program or erase operations per memory block. The table entries can consist of a triplet of voltages, i.e. one voltage for the lower page of the memory block and two for the upper page of the memory block, which is equivalent to the read voltages for the allocated word lines.
A fixed granularity of cycle counts is needed, for instance the voltage levels change every thousand cycles. The voltage levels stored in the table are chosen to maximize endurance and are determined offline by characterization of the multi-level memory device. As part of a page's meta-data, the number of P/E cycles it has been subjected to can be stored. This meta-data information is commonly stored in DRAM on the memory controller. In this case, to read a page one must retrieve the P/E cycle count from DRAM and then look up the read voltage levels from the table.
In the common systems, the same read voltage levels are used for all pages only depending on the number of P/E cycles.
Conventional methods and techniques using the above approach are described, for example, in US 2012/0239858 A1, U.S. Pat. Nos. 7,986,560 B2, 7,649,782 B2, 8,116,141 B2, US 2013/0145079 A1, and US 2013/0215682 A1 or in Threshold Voltage Distribution in MLC NAND Flash Memory: Characterization, Analysis, and Modeling by Cai et al and Using Lifetime-Aware Progressive Programming to Improve SLC NAND Flash Memory Write Endurance by Dong et al.
Accordingly, the present invention provides an improved device for selecting a read voltage level for reading data stored in a multi-level memory device.